1. Technical Field
A semiconductor device and method of manufacturing the same are disclosed in which the size of steps between memory cells and transistors can be reduced.
2. Description of the Related Art
In a manufacture process of a NAND flash memory device, a SAFG (Self-Aligned Floating Gate) method is employed. This SAFG method is a technology where a tunnel oxide film and a polysilicon layer are sequentially formed on a semiconductor substrate portions of the polysilicon layer and the tunnel oxide film disposed in an element isolation region are then removed. The semiconductor substrate is then etched in a word line direction to form a trenches in the element isolation region. The trenches are then buried or filled with an insulating material to form an element isolation film while patterning the polysilicon layer.
A manufacturing method using the SAFG method can have the following problems.
First, the SAFG method is advantageous in the word line direction, but is disadvantageous in that it is difficult to shrink the device in a bit line direction because an existing RIE mode is used. That is, in the process of etching the stack structure having a high step at the same time, which consists of Poly1/ONO/Poly2/WSi/Nitride/Oxynitride, etc., there is a difficulty in etching them using the existing technology if the design rule is small.
Second, in order to form transistors in the peripheral region, after the self-aligned floating gate and the tunnel oxide film are removed, an oxidization process for forming the gate oxide film must be repeated.
Third, the process of forming a polysilicon layer for a control gate, etching the polysilicon layer for a control gate by an etch process using a hard mask and then forming an underlying polysilicon layer for a floating gate by means of a self-aligned etch mode is advantageous in that the floating gate is aligned. This process, however, is disadvantageous in that residues are generated because of by-products since several layers are etched at the same time and there is a limit to selection of chemicals for the post cleaning.
Fourth, if the polysilicon layer for the floating gate is etched by an existing reactive ion etch (RIE) method, it is difficult to set a target etch thickness or an etch end time as an etch thickness increases due to a high or large step. Therefore, etch damage can be generated in the semiconductor substrate. It is also difficult to bury or fill between the gate lines with the insulating material since the gap between the gate lines is relatively deep.
Fifth, if the self-aligned etch process is performed in the RIE mode, etch technologies having a high selective ratio between oxide and nitride are required in order to protect the gate lines using a spacer nitride film and to form a metal contact (SAC process).
Sixth, if the SAC process is employed, there is a difficulty in lowering resistance to a target value since the area at the bottom of the metal contact reduces because of the spacer nitride film.
Seventh, a relatively thick interlayer insulating film is formed in the peripheral circuit region due to the structure of the memory cell and the transistor formed in the peripheral region and a difference in height between them. In the process of forming the contact hole, therefore, the interlayer insulating film remains in the peripheral circuit region. Accordingly, there is a problem in that the contact hole is not formed.